1. Field of the Invention
The present invention relates to a motor speed control circuit.
2. Description of the Related Art
Various electronic apparatuses have an exothermic body that generates heat when the electronic apparatus operates. To cool this exothermic body, a fan motor is usually provided. For example, in personal computers, servers and the like, the operating frequencies of the CPUs become increasingly high year by year causing the heat values of the CPUs to increase. Accordingly, a fan motor for cooling the CPU and a motor driver to drive the fan motor is usually provided in personal computers, servers and the like.
As a speed control method for fan motors, a speed servo control method has been proposed which has a PWM drive method combined therewith as shown, e.g., in FIG. 10 (refer, for example, to Japanese Patent Application Laid-Open Publication No. 2003-204692).
To describe in detail, a rotational speed detection signal obtained from a pulse generator PG of a motor 1 is supplied to an operational amplifier 7 for generating a speed voltage. The output of this operational amplifier 7 is integrated by an RC filter circuit to produce a direct-current speed voltage VV, which is applied to the inverting input terminal of a comparator 9. Furthermore, a PWM (Pulse Width Modulation) signal set by a CPU 5 is supplied to an operational amplifier 6 for generating a reference voltage. The PWM signal sets the rotational speed of the motor 1 via its duty ratio. The output of the operational amplifier 6 is integrated by an RC filter circuit to produce a direct-current reference voltage VR, which is applied to the non-inverting input terminal of the comparator 9.
The comparator 9 compares the speed voltage VV applied to the inverting input terminal and the reference voltage VR applied to the non-inverting input terminal, and produces and outputs a control signal VC as the comparing result. A motor driver 11 causes the amount of current corresponding to the control signal VC from the comparator 9 to flow through the drive coil of the motor 1 thereby controlling the rotational speed of the motor 1. Furthermore, a hall element 13 is provided for the stator of the motor 1, and the motor driver 11 controls the rotational direction of the motor 1 by switching the direction of the current flowing through the drive coil of the motor 1 on the basis of the hall element output of the hall element 13 indicating the detected position of the rotor.
As such, in order to perform speed servo control of the fan motor, as shown, e.g., in FIG. 10, there is provided circuitry that is equivalent to the operational amplifier 7 that generates the speed voltage VV indicating the detected, actual rotational speed of the motor 1, the operational amplifier 6 that generates the reference voltage VR of a level according to a motor rotational speed-specifying signal such as the PWM signal, and the comparator 9 that compares the speed voltage VV supplied from the operational amplifier 7 and the reference voltage VR supplied from the operational amplifier 6.
The configuration of the operational amplifiers 6, 7, as shown in FIG. 10 has a complementary push-pull circuit provided at the last stage for output, in which two bipolar transistors complementarily switching on/off are connected in series with a bias voltage VREG applied thereto. That is, in the operational amplifier 6, a complementary push-pull circuit of a PNP transistor T1 and an NPN transistor T2 is provided at the last stage for output, and in the operational amplifier 7, a complementary push-pull circuit of a PNP transistor T3 and an NPN transistor T4 is provided at the last stage for output.
The problem of the prior art will be explained below using as an example the case where the motor speed control system shown in FIG. 10 accelerates/decelerates the motor 1 according to the logic shown in FIG. 11. The logic of the motor driver 11 is as follows. When the reference voltage VR is lower in level than the speed voltage VV and thus the control signal VC output from the comparator 9 is at a Low level, the motor driver 11 accelerates the motor 1. On the other hand, when the reference voltage VR is higher in level than the speed voltage VV and thus the control signal VC output from the comparator 9 is at a High level, the motor driver 11 decelerates the motor 1.
As described above, the operational amplifiers 6, 7 have a complementary push-pull circuit provided at the last stage for output, in which two bipolar transistors complementarily switching on/off are connected in series with the bias voltage VREG applied thereto. Hence, the output voltage of the operational amplifiers 6, 7 is supposed to range from the bias voltage VREG to ground voltage GND. However, the above complementary push-pull circuit reduces the output voltage range of the operational amplifiers 6, 7 by a collector-to-emitter saturation voltage VCE(sat).
Accordingly, as shown in FIG. 12, the reference voltage VR for when stopping the motor 1 is set lower by the collector-to-emitter saturation voltage VCE(sat) of PNP transistor T1 of the operational amplifier 6 than the bias voltage VREG. Moreover, the reference voltage VR for when running the motor 1 at full speed is set higher by the collector-to-emitter saturation voltage VCE(sat) of NPN transistor T2 of the operational amplifier 6 than ground voltage GND.
In such a situation, consider the case where the rotational speed of the motor 1 is being lowered on the basis of the reference voltage VR for when stopping the motor 1 and thereby the level of the speed voltage VV is ascending. When the rotational speed detection signal is not produced by the pulse generator PG because the motor 1 has stopped, the speed voltage VV finally settles to be lower by the collector-to-emitter saturation voltage VCE(sat) of PNP transistor T3 of the operational amplifier 7 than the bias voltage VREG. Here, it is known that although they are of the same type in transistor characteristics, PNP transistor T1 of the operational amplifier 6 and PNP transistor T3 of the operational amplifier 7 vary in collector-to-emitter saturation voltage VCE(sat) depending on temperature, production process, or the like. This variation may cause the speed voltage VV to rise above the reference voltage VR. In this case, the problem occurs that the motor driver 11 accelerates the motor 1 according to the logic shown in FIG. 11, although being instructed to stop the motor 1.
Furthermore, in such a situation, consider the case where the rotational speed of the motor 1 is being raised on the basis of the reference voltage VR for when running the motor 1 at full speed and thereby the level of the speed voltage VV is descending. The speed voltage VV finally settles to be higher by the collector-to-emitter saturation voltage VCE(sat) of NPN transistor T4 of the operational amplifier 7 than ground voltage GND. Here, the difference in collector-to-emitter saturation voltage VCE(sat) between NPN transistor T2 of the operational amplifier 6 and NPN transistor T4 of the operational amplifier 7 may cause the speed voltage VV to go below the reference voltage VR. In this case, the problem occurs that the motor driver 11 decelerates the motor 1 according to the logic shown in FIG. 11, although being instructed to run the motor 1 at full speed.